Micro-scale interconnect device with internal heat spreader and method for fabricating same

ABSTRACT

A micro-scale interconnect device with internal heat spreader and method for fabricating same. The device includes first and second arrays of generally coplanar electrical communication lines. The first array is disposed generally along a first plane, and the second array is disposed generally along a second plane spaced from the first plane. The arrays are electrically isolated from each other. Embedded within the interconnect device is a heat spreader element. The heat spreader element comprises a dielectric material disposed in thermal contact with at least one of the arrays, and a layer of thermally conductive material embedded in the dielectric material. The device is fabricated by forming layers of electrically conductive, dielectric, and thermally conductive materials on a substrate. The layers are arranged to enable heat energy given off by current-carrying communication lines to be transferred away from the communication lines.

TECHNICAL FIELD

[0001] The present invention generally relates to micro-scale electricalinterconnect devices and the fabrication thereof. More particularly, thepresent invention relates to the integration of heat spreading elementswith such interconnect devices.

BACKGROUND ART

[0002] Micro-scale devices or systems such as integrated circuits (ICs),opto-electronic and photonic devices, micromechanical devices,micro-electro-mechanical systems (MEMS), micro-opto-electro-mechanicalsystems (MOEMS or optical MEMS), chip-based biosensors and chemosensors,microfluidic devices (e.g., labs-on-a-chip), and other articlescharacterized by micron- and sub-micron-sized features often require theuse of high-density electrical interconnect schemes for transmittingsignals. The interconnect scheme can consist of a cross-bar array ofcommunication lines located at different levels or planes of amicro-scale structure. For example, one level can contain an arrangementof parallel input lines, while another level can contain an arrangementof parallel output lines oriented orthogonal to the input lines. Any twolevels of communication lines can be electrically isolated from eachother by embedding the lines in dielectric material and/or building adielectric layer between the levels.

[0003] It is desirable to integrate interconnect schemes with thearchitecture of such micro-scale devices and, in particular, arraydevices such as DC micro-relays. However, the electrical current carriedthrough a high-density interconnect arrangement of communication linescan give rise to self-heating. Joule heating (h) is associated with theconduction of current (i) over time (t) through communication lines madefrom a material having a resistance (r), and can be expressed by Joule'slaw: h=i² rt. Joule heating gives rise to elevated temperatures in thevarious layers of a micro-scale structure and steep thermal gradients indielectric layers. The heat energy dissipated through a micro-scalestructure, particularly a MEMS device built over an interconnect scheme,can damage the components of the structure or impair the performance ofthose components. Depending on the current load, the elevatedtemperatures attained can result in thermally induced stress-relatedissues such as warping.

[0004] For example, a MEMS device can include a DC switch that utilizesa parallel-plate capacitor architecture for actuation purposes. Athermally-induced curvature in the substrate of this MEMS device couldresult in the shorting of the DC switch. As another example, in the caseof very high current loads that are likely to occur during a powersurge, the temperatures attained could be high enough to heat certainmaterials of a micro-scale device up to their melting point ortransition temperature, and thus cause destruction of the entire device.Thus, while it is desirable to integrate a high-density interconnectscheme with a micro-scale device, the inclusion of the interconnectscheme would restrict the operating range of the device and raiseconcerns about the reliability of the device.

[0005] It would therefore be advantageous to provide an interconnectdevice that is structured to reduce maximum operating temperatures,thereby enabling the interconnect device and the useful features itprovides to be integrated with a wide variety of micro-scale devices.

DISCLOSURE OF THE INVENTION

[0006] A method is provided for fabricating an interconnect device orinterconnect array-containing device wherein a heat spreader is formedas an integral part of the overall fabrication process. An interconnectdevice comprising an integral heat spreader is also provided, and issuitable for integration with any micro-scale device that could benefitfrom such integration.

[0007] According to one embodiment, a micro-scale interconnect device isprovided for transmitting electrical current or discrete signals. Thedevice comprises first and second arrays of generally coplanarelectrical communication lines and a heat spreader element. The firstarray can be disposed generally along a first plane. The second arraycan be disposed generally along a second plane spaced from the firstplane, electrically isolated from the first array. The heat spreaderelement comprises a dielectric material disposed in thermal contact withat least one of the arrays, and a layer of thermally conductive materialembedded in the dielectric material. The thermally conductive materialis electrically isolated from the first and second arrays.

[0008] According to another embodiment, a micro-scale interconnectdevice comprises a first dielectric layer, a first layer ofcommunication lines, a second dielectric layer, a thermally conductivelayer, a third dielectric layer, and a second layer of communicationlines. The first layer of communication lines can be formed on the firstdielectric layer. The second dielectric layer can be formed on the firstlayer of communication lines and on the first dielectric layer. Thethermally conductive layer can be formed on the second dielectric layer.The third dielectric layer can be formed on the thermally conductivelayer. The second layer of communication lines can be formed on thethird dielectric layer.

[0009] According to yet another embodiment, a micro-scale systemcomprises an interconnect device as described herein and a micro-scaledevice electrically communicating with one or more communication linesof the interconnect device. The micro-scale device can be any devicethat could benefit from the integration of an interconnect device withinternal heat spreading capability as disclosed herein. Non-limitingexamples of micro-scale devices include microelectronic devices andcircuitry, MEMS devices, optical devices, microfluidic devices, and thelike.

[0010] According to a method provided herein for fabricating amicro-scale device having internal heat spreading capability to reduceoperating temperature, a plurality of generally coplanar arrays ofelectrical transmission lines can be formed in a heterostructure. Athermally conductive element can be embedded in one or more dielectriclayers. The thermally conductive element can be disposed at a locationof the heterostructure where a heat transfer path can be established inresponse to a thermal gradient that is generally directed from at leastone of the arrays to the thermally conductive layer. The thermallyconductive element can be interposed between two arrays and serve as acapacitive shield.

[0011] According to another method, a first array of conductive elementscan be formed on a substrate. A first dielectric layer can be depositedon the first array. A layer of thermally conductive material can bedeposited on the first dielectric layer. A second dielectric layer canbe deposited on the layer of thermally conductive layer. A second arrayof conductive elements can be formed on the second dielectric layer.

[0012] According to yet another method, current is conducted in amicro-scale interconnect device at a reduced device operatingtemperature. The interconnect device comprises a first array ofgenerally coplanar electrical communication lines disposed generallyalong a first plane, and a second array of generally coplanar electricalcommunication lines disposed generally along a second plane that isspaced from the first plane and electrically isolated from the firstarray. The current is conducted through at least one of thecommunication lines of the first or second arrays. Heat energy given offby the current-conducting communication line is transferred away fromthe arrays by providing a heat spreader element integrated with theinterconnect device. The heat spreader element comprises a dielectricmaterial disposed in thermal contact with at least one of the arrays,and a layer of thermally conductive material embedded in the dielectricmaterial. The heat energy is directed toward the heat spreader elementin response to a thermal gradient that is created between thecurrent-conducting communication line and the heat spreader element.

[0013] Micro-scale devices fabricated according to the above-statedmethods are also provided.

[0014] It is therefore an object of the invention to provide amicro-scale interconnect device with an internal heat spreader andrelated methods of fabrication and use.

[0015] An object of the invention having been stated hereinabove, andwhich is achieved in whole or in part by the invention disclosed herein,other objects will become evident as the description proceeds when takenin connection with the accompanying drawings as best describedhereinbelow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIGS. 1A-1G are sequential cross-sectional views of aninterconnect device as it is being fabricated;

[0017]FIG. 2 is a top plan view of an array of communication lines thatcan form a part of the interconnect device;

[0018]FIG. 3 is a cross-sectional view of an interconnect deviceintegrated with a micro-scale device that includes other micro-scaledevices, systems, and/or features; and

[0019]FIG. 4 is a plot of data obtained from a comparative steady-stateelectrothermal analysis of the interconnect device with and without theinclusion of a heat spreading component.

DETAILED DESCRIPTION OF THE INVENTION

[0020] For purposes of the present disclosure, it will be understoodthat when a given component such as a layer, film, region or substrateis referred to herein as being disposed or formed “on” anothercomponent, that given component can be directly formed on the othercomponent or, alternatively, intervening components (for example, one ormore buffer, transition or lattice-matching layers, interlayers,adhesion or bonding layers, electrodes or contacts) can also be present.It will be further understood that the terms “disposed on” and “formedon” are used interchangeably to describe how a given component ispositioned or situated in relation to another component. Moreover, termssuch as “disposed on” and “formed on” are not intended to introduce anylimitations relating to particular methods of material deposition, filmgrowth, or other fabrication techniques.

[0021] For the purpose of the present disclosure, the term “layer”denotes a generally thin, two-dimensional structure having anout-of-plane thickness in the micrometer range. The term “layer” isconsidered to be interchangeable with other terms such as film, thinfilm, coating, cladding, plating, and the like.

[0022] The naming herein of any specific material compositions (e.g.,SiO₂, Cu, Au, and the like), is not intended to imply that suchmaterials are completely free of impurities, trace components, ordefects. Moreover, the material compositions identified herein are notlimited to any specific crystalline or non-crystalline microstructure.

[0023] Referring now to FIGS. 1A-1G, one method for fabricating anelectrical interconnect device, generally designated 10 in FIG. 1G, willnow be described. Referring first to FIG. 1A, a suitable substrate S isselected as a base material on which conductive and non-conductivelayers are to be formed. Substrate S can be composed of any materialcommonly employed as a substrate in micro-scale fabrication such as, forexample, silicon or a silicon-containing compound. Silicon or asilicon-containing compound is preferred because such material isreadily, commercially available at low cost, and is compatible for useas a starting substrate S on which a wide variety of commonly employedconductive and non-conductive materials can be formed by widely acceptedfabrication techniques (e.g., deposition, electroplating, and the like).In addition, depending on the specific final product contemplated,interconnect device 10 (see FIG. 1G) can be integrated with othermicro-scale devices or circuitry that require a substrate havingsemi-conducting properties, in which case a silicon substrate common toboth interconnect device 10 and one or more other micro-scale componentsmight be desirable.

[0024] It will be noted that the following fabrication process caninclude any intermediate process steps considered necessary or desirableby persons skilled in the art to be carried out between the adding ofspecific layers to substrate S. Such intermediate process steps caninclude surface micromachining techniques such as chemomechanicalpolishing (CMP) to planarize, clean, or otherwise prepare certain layersfor subsequent material-additive steps; drilling or etching techniquesfor creating vias, cavities or apertures through certain layers whereneeded; the addition and subsequent removal of transient layers such asphotoresist materials and their residue; cleaning steps such as chemicalstripping, plasma etching and the like; and other surface preparationprocedures. The details of these intermediate processes, theappropriateness of their use during any stage of the interconnectfabrication process, and the equipment required, are generally known topersons skilled in the art and hence are not described further herein.

[0025] With continuing reference to FIG. 1A, a first dielectricisolation layer D1 is formed on substrate S. Preferably, firstdielectric isolation layer D1 includes a suitable dielectric materialexhibiting a low dielectric constant (low-k) such as, for example,silicon dioxide (SiO₂). As will be appreciated by persons skilled in theart, the technique utilized for forming first dielectric isolation layerD1 typically will depend at least in part on the material comprisingfirst dielectric isolation layer D1. In the case of SiO₂, a depositionprocess is commonly employed. A wide variety of viable depositionprocesses for forming dielectric layers or films are known to personsskilled in the art, and thus need not be described in detail herein.Alternative processes such as thermal oxidation might also beappropriate.

[0026] In an alternative embodiment, instead of including asemiconductor material, substrate S can be a bulk structural layer thatis dielectric. Non-limiting examples of dielectric materials suitablefor use as a bulk structural layer include silica, various glasses,sapphire, nitrides of silicon, and the like. In the case where substrateS is composed of a dielectric material, the addition of first dielectricisolation layer D1 is not required.

[0027] Referring to FIG. 1B, a first electrically conductive layer M1 isformed on first dielectric isolation layer D1. First electricallyconductive layer M1 can be composed of any electrically conductivematerial. Preferably, first electrically conductive layer M1 is composedof a metal exhibiting suitable electrical conductivity such as, forexample, copper (Cu). As will be appreciated by persons skilled in theart, the technique utilized for forming first electrically conductivelayer M1 will typically depend at least in part on the materialcomprising first electrically conductive layer M1 and its compatibilitywith the material selected for first dielectric isolation layer D1. Inthe case of copper, an electroplating process is commonly employed. Itis further appreciated by persons skilled in the art, however, that awide variety of deposition processes might alternatively be utilized forforming metallic layers on dielectric layers. The particular techniquesfor laying down metals in a micro-scale environment are generally knownand thus need not be described in detail herein.

[0028] As shown in FIG. 1B, after film formation, first electricallyconductive layer M1 is then patterned by any suitable technique, such asmasking followed by etching as understood by persons skilled in the art,to form a set of first transmission or communication lines COM1. Whilethe cross-section of only one communication line COM1 is illustrated inFIG. 1B, it will be appreciated by persons skilled in the art that firstelectrically conductive layer M1 can preferably be patterned to form aplurality of spaced-apart communication lines COM1 on first dielectricisolation layer D1 to provide multiple routes for electrical signals, asexemplified in the cross-bar configuration illustrated in FIG. 2.

[0029] Referring to FIG. 1C, a second dielectric isolation layer D2 isformed on the pattern of first communication lines COM1 and on theexposed regions of first dielectric isolation layer D1. Like firstdielectric isolation layer D1, second dielectric isolation layer D2 ispreferably composed of a suitable low-k dielectric material such asSiO₂. Referring to FIG. 1D, a thermally conductive layer HS is thenformed on second dielectric isolation layer D2 to serve as a heatspreader. Preferably, the out-of-plane thickness of thermally conductivelayer HS can range from approximately 0.1 to approximately 1 microns.Thermally conductive layer HS can include any material that is thermallyconductive such as, for example, gold (Au), copper, aluminum (Al), anddiamond. In the case of gold, a physical deposition technique such assputtering can be employed to form thermally conductive layer HS,although alternative techniques such as electroplating could beemployed. Referring to FIG. 1E, a third dielectric isolation layer D3 isformed on thermally conductive layer HS. Like first and seconddielectric isolation layers, third dielectric isolation layer D3 ispreferably composed of a suitable low-k dielectric material such asSiO₂.

[0030] Referring to FIG. 1F, a second electrically conductive layer M2is formed on third dielectric isolation layer D3. Like firstelectrically conductive layer M1, second electrically conductive layerM2 is preferably composed of a metal such as copper. Second electricallyconductive layer M2 is then patterned by any suitable technique to forma second set of communication lines COM2, which in typical embodimentsare arranged generally orthogonally relative to the first set ofcommunication lines COM1 formed from first electrically conductive layerM1. While a section of only one communication line COM2 of secondelectrically conductive layer M2 is illustrated in FIG. 1F, it will beappreciated by persons skilled in the art that second electricallyconductive layer M2 is preferably patterned to form a plurality ofspaced-apart communication lines COM2 on third dielectric isolationlayer D3, as shown in FIG. 2.

[0031] Referring to FIG. 1G, the fabrication of interconnect device 10is completed by forming a fourth dielectric isolation layer D4 on thepattern of second communication lines COM2. Like first, second and thirddielectric isolation layers D1-D3, fourth dielectric isolation layer D4is preferably composed of a suitable low-k dielectric material such assiO₂.

[0032] For the exemplary embodiment presently being described, FIGS.1A-1G show the conformal deposition of dielectric isolation layersD2-D4, thermally conductive layer HS, and second electrically conductivelayer M2 around the shape of the first communication lines COM1 formedfrom first electrically conductive layer M1. As an alternative, some orall of these layers could be planarized. For instance, second dielectricisolation layer D2 could be deposited and planarized to a specificthickness above first communication lines COM1. Second dielectricisolation layer D2 could be planarized by a process such aschemical-mechanical polishing (CMP). Thermally conductive layer HS wouldthen be deposited on second dielectric isolation layer D2, which definesa specific distance to first electrically conductive layer M1. Thirddielectric isolation layer D3 would then be deposited on thermallyconductive layer HS. Third dielectric layer D3 and thermally conductivelayer HS are largely planar because they are deposited on a planarsurface. Second electrically conductive layer M2 would be deposited onthird dielectric isolation layer D3, which is a planar surface. Fourthdielectric isolation layer D4 is deposited on third dielectric isolationlayer D3 and second electrically conductive layer M2 and planarized to aspecific thickness above second electrically conductive layer M2. Fourthdielectric isolation layer D4 could be planarized by methods such aschemical-mechanical polishing (CMP). The benefits of the heat spreaderHS layer are realized for a planar process or a conformal process, ifthe widths of communication lines COM1 and second communication linesCOM2 lines are large relative to their thickness. In either case, mostof the heat flow would be between the first electrically conductivelayer M1 and second electrically conductive layer M2 rather thanlaterally between first communication lines COM1 or second communicationlines COM2. The goal of the heat spreader is to accomplish driving theheat flow laterally and reducing the localized temperature, especiallyby driving heat energy away from likely hot spots such as regions wherecommunication lines COM1 and COM2 cross each other. If the width andthickness of the first electrically conductive layer M1 and secondelectrically conductive layer M2 lines are of comparable magnitude, theconformal process might provide greater heat spreading (localtemperature reduction) than the planarized case.

[0033] It will be noted that FIG. 1G is a cross-sectional depiction of aportion of the resulting interconnect device 10. In practice, ahigh-density array or grid of several rows and columns of communicationlines COM1 and COM2 is formed from first and second electricallyconductive layers M1 and M2, as exemplified in the cross-barconfiguration illustrated in FIG. 2. First communication lines COM1 aredisposed generally along a first plane and second communication linesCOM2 are disposed generally along a second plane that is spaced from thefirst plane. In one embodiment, the spacing between first communicationlines COM1 and second communication lines COM2 can range fromapproximately 3 to approximately 8 microns. The spacing between eachadjacent, co-planar pair of first communication lines COM1, and betweeneach adjacent, co-planar pair of second communication lines COM2, isindicated by a distance d in FIG. 2. Distance d can range fromapproximately 25 to approximately 250 microns, and preferably isapproximately 125 microns. In one embodiment, distance d between alladjacent, coplanar pairs of communication lines COM1 and COM2 isuniform. By evenly spacing communication lines COM1 and COM2 in thismanner, the distribution of heat energy through interconnect device 10is rendered more uniform which, for large interconnect densities, canassist in reducing the maximum operating temperature in addition to theintegration of thermally conductive layer HS. In one embodiment, thewidth of each communication line COM1 and COM2 across the layer on whichit is formed can range from approximately 10 to approximately 100microns, and preferably is approximately 100 microns. The thickness ofeach communication line COM1 and COM2 on its corresponding layer canrange from approximately 1 to approximately 5 microns, and preferably isapproximately 3 microns The thickness of first dielectric isolationlayer D1 is typically 0.5 to 1 micron. The thickness of seconddielectric isolation layer D2 is typically 1 to 5 microns, andpreferably is approximately 1.5 microns. The thickness of thirddielectric isolation layer D3 is typically 1 to 5 microns, andpreferably is approximately 1.5 microns. The thickness of fourthdielectric isolation layer D4 is typically 1 to 5 microns, andpreferably is approximately 3 microns.

[0034] In a cross-bar configuration such as illustrated in FIG. 2, onedesign goal enabled by the invention is to minimize the resistance ofthe communication lines COM1 and COM2 and minimize the heating thatresults from a self-heating process. Additionally, the dimensions of thedielectric and conductive layers are optimized with regard toresistance, heating, temperature, and capacitive coupling. Additionally,the volume fraction of the electrically conductive layers to thedielectric layers is optimized to minimize the stress and curvature thatare developed in substrate S with regard to residual stress fieldswithin the layers, with regard to differences in thermal coefficients ofexpansion, or with regard to temperature gradients through the layersand substrate S.

[0035] It can be seen from FIG. 1G that thermally conductive layer HSconstituting the heat spreader is sandwiched between first and secondcommunication lines COM1 and COM2 formed from first and secondelectrically conductive layers M1 and M2, respectively, as a buried,integral component of interconnect device 10. Second and thirddielectric isolation layers D2 and D3 electrically isolate thermallyconductive layer HS from first and second electrically conductive layersM1 and M2, respectively. First dielectric isolation layer D1electrically isolates the as-built conductive/non-conductiveheterostructure of interconnect device 10 from its substrate S. Fourthdielectric isolation layer D4 electrically isolates second communicationlines COM2 of second electrically conductive layer M2 from any circuitryor devices fabricated on interconnect device 10.

[0036] As described hereinabove, thermally conductive layer HS ispreferably composed of a metal such as gold, and thus preferably is alsoelectrically conductive. Accordingly, it will be noted that any two ofthe three metal layers illustrated in FIG. 1G could serve as first andsecond electrically conductive layers M1 and M2 for forming first andsecond communication lines COM1 and COM2, with the remaining third metallayer serving as thermally conductive layer HS and thus as the heatspreader. However, in the embodiment illustrated in FIG. 1G in whichthermally conductive layer HS is sandwiched between first and secondcommunication lines COM1 and COM2, thermally conductive layer HS couldadditionally function as a capacitive shield. Hence, by providing propergrounding to thermally conductive layer HS, out-of-plane capacitivecoupling between first and second communication lines COM1 and COM2could be reduced in at least some embodiments. Additionally, a thermallyconductive layer HS added between substrate S and the communicationlines COM1 and COM2 will block the electromagnetic coupling to substrateS. The electrostatic shielding is applicable for capacitive coupling andRF pads for application at “low frequencies”. In this example ofcapacitive coupling, thermally conductive layer HS can be largelyunpatterned with the exception of regions where connections will beestablished between first and second communication lines COM1 and COM2.Additionally, thermally conductive layer HS can be patterned to reducethe total amount of metalization used while maintaining the thermaladvantage. Additionally, thermally conductive layer HS will need to bepatterned for it to provide shielding when inductors are part ofsubstrate S. The shield needs to be patterned to limit the effect ofeddy currents, which produce opposing magnetic fields resulting inreduced energy storage and reduced Q (quality factor). The design of theshield for inductor applications is known to those skilled in the artand is not described further herein.

[0037] Referring now to FIG. 3, a micro-scale system, generallydesignated 100, includes the heterostructure of interconnect device 10as integrated with any other micro-scale device, circuitry, orinstrument fabricated typically on the heterostructure at device region105A, and/or at device regions 105B, 105C, and 105D. As non-limitingexamples, device regions 105A, 105B, 105C, and/or 105D could representmicroelectronic devices or integrated circuits having active and/orpassive circuit elements such as transistors, resistors, capacitors, MOSor related circuit components, contacts, electrodes, and electricalleads; opto-electronic and photonic devices such as windows, lenses,light-emitting diodes (LEDs), laser diodes (LDs), photodiode arrays,mirrors, filters, flat-panel displays, and waveguides; micromechanicaldevices such as deflectable cantilevers and membranes, andencapsulating, structural, or packaging components; MEMS devices such asmicrorelays, micromotors, gyroscopes, accelerometers, andthermally-induced components and transducers in general; MOEMS devicessuch as movable optical shutters, attenuators, electromagnetic radiationdetectors, and switches; chip-based biosensors and chemosensors; andmicrofluidic devices such as labs-on-a-chip (LoC), micro-total analysissystems (μ-TAS), or other devices having microfluidic-related featuressuch as micropumps, microchannels, reservoirs, sample stamping arrays,and inkjet-type nozzles.

[0038] Referring now to FIG. 4, the results of a comparative,steady-state electro-thermal analysis performed on a unit cell areillustrated. The unit cell is representative of a DC switch array havingan interconnect scheme as illustrated in FIG. 1G. The dielectricmaterial considered for the isolation layers was silica, the metalconsidered for the electrically conductive layers was copper, and themetal considered for the thermally conductive heat spreading layer wasgold. As indicated in FIG. 4, the width of the unit cell is 40 micronsand the thickness (t_(i)) is varied along the horizontal axis of thedata plot. As further indicated in FIG. 4, maximum operating temperatureis plotted as a function of unit cell thickness for three separatecases: a heat spreader thickness of zero (i.e., no heat spreader), 0.1micron, and 1 micron. It can be observed from FIG. 4 that the presenceof a 1-micron thick heat spreader significantly reduces maximumtemperature reached in the unit cell at progressively greater unit cellthicknesses. Moreover, FIG. 4 shows that the gains observed due to theincorporation of the heat spreader are more significant moving down tothinner transmission lines. Also, the reduction obtained would besignificant at even higher current magnitudes due the current-squareddependence of the Joule Heating effect.

[0039] It will be understood that various details of the invention maybe changed without departing from the scope of the invention.Furthermore, the foregoing description is for the purpose ofillustration only, and not for the purpose of limitation—the inventionbeing defined by the claims.

What is claimed is:
 1. A method for fabricating a micro-scale devicehaving internal heat spreading capability to reduce operatingtemperature, comprising the steps of forming a plurality of generallycoplanar arrays of electrical transmission lines in a heterostructure,and embedding a thermally conductive element in one or more dielectriclayers at a location of the heterostructure where a heat transfer pathcan be established in response to a thermal gradient generally directedfrom at least one of the arrays to the thermally conductive layer. 2.The method according to claim 1 wherein adjacent coplanar transmissionlines of each array are separated from each other by a distance rangingfrom approximately to approximately 250 microns.
 3. The method accordingto claim 1 comprising forming the arrays, the thermally conductiveelement, and the dielectric layers on an electrically isolatedsubstrate.
 4. The method according to claim 1 wherein the plurality ofarrays comprises a first array and a second array, and the embeddedthermally conductive element is interposed between the first and secondarrays.
 5. The method according to claim 4 wherein the thermallyconductive element reduces capacitive coupling between the first andsecond arrays.
 6. The method according to claim 1 wherein the thermallyconductive element has an out-of-plane thickness ranging fromapproximately 0.1 to approximately 1 microns.
 7. The method according toclaim 1 wherein the thermally conductive element comprises a materialselected from the group consisting of gold, copper, aluminum anddiamond.
 8. A micro-scale device fabricated according to the method ofclaim
 1. 9. A method for fabricating a micro-scale device havinginternal heat spreading capability to reduce operating temperature,comprising the steps of: (a) forming a first array of conductiveelements on a substrate; (b) depositing a first dielectric layer on thefirst array; (c) depositing a layer of thermally conductive material onthe first dielectric layer; (d) depositing a second dielectric layer onthe layer of thermally conductive material; and (e) forming a secondarray of conductive elements on the second dielectric layer.
 10. Amicro-scale device fabricated according to the method of claim
 9. 11. Amethod for conducting current in a micro-scale interconnect device at areduced device operating temperature, comprising the steps of: (a)conducting current in a micro-scale interconnect device comprising afirst array of generally coplanar electrical communication linesdisposed generally along a first plane, and a second array of generallycoplanar electrical communication lines disposed generally along asecond plane spaced from the first plane and electrically isolated fromthe first array, wherein the current is conducted through at least oneof the communication lines of the arrays; and (b) causing heat energygiven off by the at least one current-conducting communication line tobe transferred away from the arrays by providing a heat spreader elementintegrated with the interconnect device, the heat spreader elementcomprising a dielectric material disposed in thermal contact with atleast one of the arrays, and a layer of thermally conductive materialembedded in the dielectric material, whereby the heat energy is directedtoward the heat spreader element in response to a thermal gradientcreated between the at least one current-conducting communication lineand the heat spreader element.